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Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

  • Computer Engineering: 100%

Research Areas

  • Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)
Andreas Steininger

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics, Fault Injection, trustworthy systems, sustainable computing, computer engineering

Roles

  • Associate Professor
    Embedded Computing Systems, E191-02
  • Doctoral School
    Director
  • Curriculum Commission for Computer Engineering
    Principal Member

Contact

2024W

2025S

 

2024

2023

2022

  • ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons / Prabakaran, B. S., Fasching, F., Schreib, J., Steininger, A., & Shafique, M. (2022). ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. arXiv. https://doi.org/10.34726/3642
    Download: PDF (2.02 MB)
  • Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults / Elshehaby, R., & Steininger, A. (2022). Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. https://doi.org/10.34726/4047
    Download: PDF (381 KB)
  • SET Hardened Derivatives of QDI Buffer Template / Tabassam, Z., & Steininger, A. (2022). SET Hardened Derivatives of QDI Buffer Template. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. https://doi.org/10.34726/3944
    Download: PDF (467 KB)
  • Towards Resilient QDI Pipeline Implementations / Tabassam, Z., & Steininger, A. (2022). Towards Resilient QDI Pipeline Implementations. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 657–664). IEEE. https://doi.org/10.34726/3942
    Download: PDF (597 KB)
  • AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages / Tabassam, Z., Naqvi, S. R., & Steininger, A. (2022). AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 32–37). IEEE. https://doi.org/10.34726/3941
    Download: PDF (435 KB)
  • enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks / Colucci, A., Steininger, A., & Shafique, M. (2022). enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 5155–5162). https://doi.org/10.1109/IROS47612.2022.9982181

2021

  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. https://doi.org/10.1016/j.microrel.2021.114088
    Download: PDF (1.46 MB)
  • An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / Behal, P., Huemer, F. F., Najvirt, R., & Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy. https://doi.org/10.34726/4044
    Download: PDF (506 KB)
  • Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., & Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 25–33). IEEE. https://doi.org/10.34726/3945
    Download: PDF (717 KB)
  • Input/Output-Interlocking for Fault Mitigation in QDI Pipelines / Tabassam, Z., Behal, P., Najvirt, R., & Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip) (pp. 17–20). https://doi.org/10.34726/3943
    Download: PDF (267 KB)
  • Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines / Elshehaby, R., & Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. https://doi.org/10.34726/4046
    Download: PDF (497 KB)
  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120(114088), 114088. https://doi.org/10.1016/j.microrel.2021.114088
  • Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses / Maier, J., Hartl-Nesic, C., & Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. https://doi.org/10.1109/tcsi.2021.3130349
  • Foreword / Sekanina, L., Shafique, M., Krstic, M., Steininger, A., & Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE. https://doi.org/10.1109/ddecs52668.2021.9417019

2020

  • Sorting Network based Full Adders for QDI Circuits / Huemer, F. F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4042
    Download: PDF (280 KB)
  • Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / Duer, W., & Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, Serbia. Ieee Cs. https://doi.org/10.1109/ddecs50862.2020.9095577
  • Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F. F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4043
    Download: PDF (1.76 MB)
  • Timing Domain Crossing using Muller Pipelines / Huemer, F. F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. https://doi.org/10.34726/4041
    Download: PDF (330 KB)
  • On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / Elshehaby, R., & Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. https://doi.org/10.34726/4045
    Download: PDF (462 KB)
  • Welcome Message: ASYNC 2020 / Brunvand, E., Stevens, K., Moreira, M., & Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society. https://doi.org/10.1109/async49171.2020.00005

2019

  • A Systematic Approach to Clock Failure Detection / Steininger, A., & Schwendinger, M. (2019). A Systematic Approach to Clock Failure Detection. In 2019 Austrochip Workshop on Microelectronics (Austrochip). Austrochip Workshop on Microelectronics, Wien, Austria. https://doi.org/10.1109/austrochip.2019.00018
    Project: Intel CARS (2017–2019)
  • Efficient Metastability Characterization for Schmitt-Triggers / Maier, J., & Steininger, A. (2019). Efficient Metastability Characterization for Schmitt-Triggers. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 25th IEEE International Symposium on Asynchronous Circuits and Systems, Hirosaki, Japan. https://doi.org/10.1109/ASYNC.2019.00024
    Download: PDF (799 KB)
  • Sustainable Security & Safety: Challenges and Opportunities / Paverd, A., Völp, M., Brasser, F., Schunter, M., Asokan, N., Sadeghi, A.-R., Esteves-Verissimo, P., Steininger, A., & Holz, T. (2019). Sustainable Security & Safety: Challenges and Opportunities. In M. Asplund & M. Paulitsch (Eds.), Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019) (p. 13). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.CERTS.2019.4
    Project: Intel CARS (2017–2019)
  • An Experimental Study of Metastability-Induced Glitching Behavior / Polzer, T., Huemer, F., & Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. https://doi.org/10.1142/s0218126619400061
  • Special Issue "Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018" / Krstic, M., Jones, I., Steininger, A., & Függer, M. (2019). Special Issue “Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018.” Journal of Low Power Electronics and Applications, 9(2), 2. http://hdl.handle.net/20.500.12708/143834
  • Novel Approaches for Efficient Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. https://doi.org/10.3390/jlpea9020016

2018

  • Refined Metastability Characterization Using a Time-to-Digital Converter / Polzer, T., Huemer, F., & Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. https://doi.org/10.1016/j.microrel.2017.11.017
  • Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / Huemer, F., Polzer, T., & Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/ddecs.2018.00032
  • State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
    Project: Intel CARS (2017–2019)
  • Advanced Delay-Insensitive 4-Phase Protocols / Huemer, F., & Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/austrochip.2018.8520702
  • Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/async.2018.00014

2017

  • Foreword / Steininger, A., Pawlak, A., & Stopjakova, V. (2017). Foreword. Journal of Circuits, Systems, and Computers, 26(08), Article 1702001. https://doi.org/10.1142/s0218126617020017
  • Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, Germany. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
  • Setup for an Experimental Study of Radiation Effects in 65nm CMOS / Fritz, B., Veeravalli, V. S., Steininger, A., & Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. https://doi.org/10.1109/dsd.2017.60
  • A Model for the Metastability Delay of Sequential Elements / Polzer, T., & Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. https://doi.org/10.1142/s0218126617400102
  • A versatile architecture for long-term monitoring of single-event transient durations / Savulimedu Veeravalli, V., Steininger, A., & Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. https://doi.org/10.1016/j.micpro.2017.07.007
  • A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., & Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). http://hdl.handle.net/20.500.12708/57265
  • Measuring Metastability with Free-Running Clocks / Najvirt, R., Polzer, T., & Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.18

2016

  • The Metastable Behavior of a Schmitt-Trigger / Steininger, A., Maier, J., & Najvirt, R. (2016). The Metastable Behavior of a Schmitt-Trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Porto Alegre, Brazil. IEEE. https://doi.org/10.1109/ASYNC.2016.19
    Download: PDF (503 KB)
  • Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? / Steininger, A., Najvirt, R., & Maier, J. (2016). Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? In 2016 Euromicro Conference on Digital System Design (DSD). 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus. IEEE. https://doi.org/10.1109/DSD.2016.56
    Download: PDF (347 KB)
  • Fifty Shades of Synchrony / Steininger, A. (2016). Fifty Shades of Synchrony. In A. Mokhov (Ed.), This Asynchronous Woirld (pp. 294–300). Newcastle University. http://hdl.handle.net/20.500.12708/29323
  • A General Approach for Comparing Metastable Behavior of Digital CMOS Gates / Polzer, T., & Steininger, A. (2016). A General Approach for Comparing Metastable Behavior of Digital CMOS Gates. In Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/56886
  • Study of a Delayed Single-Event Effect in the Muller C-element / Veeravalli, V. S., & Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, EU. http://hdl.handle.net/20.500.12708/56885
    Project: EASET (2014–2017)
  • Design and Physical Implementation of a Target ASIC for SET Experiments / Veeravalli, V. S., & Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. http://hdl.handle.net/20.500.12708/56884
    Project: EASET (2014–2017)
  • A Programmable Delay Line for Metastability Characterization in FPGAs / Polzer, T., Huemer, F., & Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56883
  • A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / Huemer, F., Lechner, J., & Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). http://hdl.handle.net/20.500.12708/56881

2015

  • Building reliable systems-on-chip in nanoscale technologies / Steininger, A., Zimmermann, H., Jantsch, A., Hofbauer, M., Schmid, U., Schweiger, K., & Savulimedu Veeravalli, V. (2015). Building reliable systems-on-chip in nanoscale technologies. Elektrotechnik Und Informationstechnik : E & i, 132(6), 301–306. https://doi.org/10.1007/s00502-015-0319-0
  • A Composable Real-Time Architecture for Replicated Railway Applications / Resch, S., Steininger, A., & Scherrer, C. (2015). A Composable Real-Time Architecture for Replicated Railway Applications. Journal of Systems Architecture, 61(9), 472–485. https://doi.org/10.1016/j.sysarc.2015.04.003
  • Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes / Huemer, F., Schütz, M., & Steininger, A. (2015). Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56350
  • A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols / Schütz, M., Huemer, F., & Steininger, A. (2015). A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56349
  • Containment of Metastable Voltages in FPGAs / Najvirt, R., Polzer, T., Beck, F., & Steininger, A. (2015). Containment of Metastable Voltages in FPGAs. In 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/56351
  • A Versatile and Reliable Glitch Filter for Clocks / Najvirt, R., & Steininger, A. (2015). A Versatile and Reliable Glitch Filter for Clocks. In 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (p. 8). http://hdl.handle.net/20.500.12708/56360
  • Can we trust SET Injection Models? / Veeravalli, V. S., & Steininger, A. (2015). Can we trust SET Injection Models? In MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (p. 6). http://hdl.handle.net/20.500.12708/56359
  • Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes / Lechner, J., Steininger, A., & Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). http://hdl.handle.net/20.500.12708/56358
  • Reliable and Continuous Measurement of SET Pulse Widths / Veeravalli, V. S., & Steininger, A. (2015). Reliable and Continuous Measurement of SET Pulse Widths. In 18th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/56354
  • A Pausible Clock with Crystal Oscillator Accuracy / Najvirt, R., & Steininger, A. (2015). A Pausible Clock with Crystal Oscillator Accuracy. In 22nd European Conference on Circuit Theory and Design (p. 4). http://hdl.handle.net/20.500.12708/56356
  • Enhanced Metastability Characterization based on AC Analysis / Polzer, T., & Steininger, A. (2015). Enhanced Metastability Characterization based on AC Analysis. In 18th Euromicro Conference on Digital System Design (p. 9). http://hdl.handle.net/20.500.12708/56353
  • How to Synchronize a Pausible Clock to a Reference / Najvirt, R., & Steininger, A. (2015). How to Synchronize a Pausible Clock to a Reference. In 21st IEEE International Symposium on Asynchronous Circuits and Systems (p. 8). http://hdl.handle.net/20.500.12708/56348
  • On the Appropriate Handling of Metastable Voltages in FPGAs / Polzer, T., Najvirt, R., Beck, F., & Steininger, A. (2015). On the Appropriate Handling of Metastable Voltages in FPGAs. Journal of Circuits, Systems, and Computers, 25(03), 1640020. https://doi.org/10.1142/s021812661640020x
  • Fault-tolerant Distributed Systems in Hardware / Dolev, D., Függer, M., Lenzen, C., Schmid, U., & Steininger, A. (2015). Fault-tolerant Distributed Systems in Hardware. Bulletin of the EATCS, 2(116), 43. http://hdl.handle.net/20.500.12708/151760
  • Measuring the Distribution of Metastable Upsets over Time / Polzer, T., & Steininger, A. (2015). Measuring the Distribution of Metastable Upsets over Time. In Measuring the Distribution of Metastable Upsets over Time (p. 8). http://hdl.handle.net/20.500.12708/56352

2014

  • Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic / Maier, J., & Steininger, A. (2014). Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (pp. 33–38). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/DDECS.2014.6868759
    Download: PDF (266 KB)
  • Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip / Dolev, D., Függer, M., Posch, M., Schmid, U., Steininger, A., & Lenzen, C. (2014). Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. Journal of Computer and System Sciences, 80(4), 860–900. https://doi.org/10.1016/j.jcss.2014.01.001
  • Runtime verification of microcontroller binary code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2014). Runtime verification of microcontroller binary code. Science of Computer Programming, 80, 109–129. https://doi.org/10.1016/j.scico.2012.10.015
  • Equivalence of clock gating and synchronization with applicability to GALS communication / Najvirt, R., & Steininger, A. (2014). Equivalence of clock gating and synchronization with applicability to GALS communication. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain, EU. IEEE. https://doi.org/10.1109/patmos.2014.6951873
  • Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC / Veeravalli, V. S., & Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. https://doi.org/10.1109/austrochip.2014.6946318
    Project: EASET (2014–2017)
  • Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example / Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., & Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Non-EU. IEEE. https://doi.org/10.1109/iccd.2014.6974663
    Project: EASET (2014–2017)
  • A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments / Naqvi, S. R., & Steininger, A. (2014). A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments. In Proceedings Design Automation &Test in Europe (p. 6). http://hdl.handle.net/20.500.12708/55132
  • Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum / Anghel, L., Veeravalli, V. S., Alexandrescu, D., Steininger, A., Schneider, K., & Costenaro, E. (2014). Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55131
  • Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation / Veeravalli, V. S., & Steininger, A. (2014). Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55130
  • Architecture for monitoring SET propagation in 16-bit Sklansky adder / Veeravalli, V. S., & Steininger, A. (2014). Architecture for monitoring SET propagation in 16-bit Sklansky adder. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783354
  • Measuring SET pulsewidths in logic gates using digital infrastructure / Veeravalli, V. S., Steininger, A., & Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783331
  • Protection of Muller-Pipelines from transient faults / Naqvi, S. R., Lechner, J., & Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783315

2013

  • An infrastructure for accurate characterization of single-event transients in digital circuits / Veeravalli, V. S., Polzer, T., Schmid, U., Steininger, A., Hofbauer, M., Schweiger, K., Dietrich, H., Schneider-Hornstein, K., Zimmermann, H., Voss, K.-O., Merk, B., & Hajek, M. (2013). An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocessors and Microsystems, 37, 772–791. http://hdl.handle.net/20.500.12708/156041
  • Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation / Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2013). Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation. IEEE Transactions on Nuclear Science, 60(4), 2640–2646. http://hdl.handle.net/20.500.12708/156043
  • SET Propagation in Micropipelines / Polzer, T., & Steininger, A. (2013). SET Propagation in Micropipelines. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). http://hdl.handle.net/20.500.12708/54998
  • Metastability Characterization for Muller C-Elements / Polzer, T., & Steininger, A. (2013). Metastability Characterization for Muller C-Elements. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). http://hdl.handle.net/20.500.12708/55023
  • FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution / Dolev, D., Függer, M., Hofstätter, M., Lenzen, C., Perner, M., Posch, M., Schmid, U., Sigl, M., & Steininger, A. (2013). FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution. Poster Session at the CSAIL Industry Affiliates Program (CSAIL-IAP) Annual Meeting, Cambridge, MA, USA, Non-EU. http://hdl.handle.net/20.500.12708/85710
  • Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation / Hofbauer, M., Schweiger, K., Gaberl, W., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2013). Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation. IEEE Nuclear and Space Radiation Effects Conference (NSREC), San Francisco, California (USA), Non-EU. http://hdl.handle.net/20.500.12708/85741
  • Digital Late-Transition Metastability Simulation Model / Polzer, T., & Steininger, A. (2013). Digital Late-Transition Metastability Simulation Model. In Proceedings of the 16th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/55024
  • An Approach for Efficient Metastability Characterization of FPGAs through the Designer / Polzer, T., & Steininger, A. (2013). An Approach for Efficient Metastability Characterization of FPGAs through the Designer. In 19th IEEE International Symposium on Asynchronous Circuits and Systems (p. 9). http://hdl.handle.net/20.500.12708/55021
  • A Multi-Credit Flow Control Scheme for Asynchronous NoCs / Naqvi, S. R., Najvirt, R., & Steininger, A. (2013). A Multi-Credit Flow Control Scheme for Asynchronous NoCs. In Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/55006
  • Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs / Najvirt, R., Naqvi, S. R., & Steininger, A. (2013). Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). http://hdl.handle.net/20.500.12708/55005
  • Particle Strikes in C-Gates: Relevance of SET Shapes / Najvirt, R., Veeravalli, V. S., & Steininger, A. (2013). Particle Strikes in C-Gates: Relevance of SET Shapes. In Proceedings of the MEDIAN Workshop 2013 (p. 4). http://hdl.handle.net/20.500.12708/55003
  • Performance of Radiation Hardening Techniques under Voltage and Temperature Variations / Veeravalli, V. S., & Steininger, A. (2013). Performance of Radiation Hardening Techniques under Voltage and Temperature Variations. In Proc. 2013 IEEE Aerospace Conference (p. 6). http://hdl.handle.net/20.500.12708/55004
  • Software Composability and Mixed Criticality for Triple Modular Redundant Architectures / Resch, S., Steininger, A., & Scherrer, C. (2013). Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. In Proceedings of the 2013 SASSUR Workshop (p. 4). http://hdl.handle.net/20.500.12708/55002
  • An SET Tolerant Tree Arbiter Cell / Naqvi, S. R., Steininger, A., & Lechner, J. (2013). An SET Tolerant Tree Arbiter Cell. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). http://hdl.handle.net/20.500.12708/55001
  • Muller C-Element Metastability Containment / Polzer, T., Steininger, A., & Lechner, J. (2013). Muller C-Element Metastability Containment. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 103–112). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54509

2012

  • Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K.-O., Merk, B., Schmid, U., & Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain. IEEE Transactions on Nuclear Science, 59(6), 2778–2784. https://doi.org/10.1109/tns.2012.2223233
  • Reliable Gateway for Radiation Experiments on a VLSI Chip / Fritz, B., Veeravalli, V. S., & Steininger, A. (2012). Reliable Gateway for Radiation Experiments on a VLSI Chip. In Austrochip 2012 (pp. 65–70). http://hdl.handle.net/20.500.12708/54571
  • LFSR Implementation Using C-Elements / Veeravalli, V. S., & Steininger, A. (2012). LFSR Implementation Using C-Elements. In MEMICS 2012 (pp. 73–83). http://hdl.handle.net/20.500.12708/54572
  • A Runtime Verification Unit for Microcontrollers / Reinbacher, T., Horauer, M., & Steininger, A. (2012). A Runtime Verification Unit for Microcontrollers. In System, Software, SoC and Silicon Debug Conference (S4D), 2012 (pp. 1–6). http://hdl.handle.net/20.500.12708/54566
    Project: CEVTES (2010–2013)
  • Parallel Runtime Verification of Temporal Properties for Embedded Software / Reinbacher, T., Geist, J., Moosbrugger, P., Horauer, M., & Steininger, A. (2012). Parallel Runtime Verification of Temporal Properties for Embedded Software. In Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on (pp. 224–231). http://hdl.handle.net/20.500.12708/54567
    Project: CEVTES (2010–2013)
  • Monitoring Single Event Transient Effects in Dynamic Mode / Veeravalli, V. S., & Steininger, A. (2012). Monitoring Single Event Transient Effects in Dynamic Mode. In 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012) (pp. 51–54). http://hdl.handle.net/20.500.12708/54568
  • Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K. O., Merk, B., Schmid, U., & Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain. Nuclear and Space Radiation Effects Conference (NSREC), Miami, FL, USA, Non-EU. http://hdl.handle.net/20.500.12708/89963
  • Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach / Milbredt, P., Glass, M., Lukasiewycz, M., Steininger, A., & Teich, J. (2012). Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach. In Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) Proceedings (pp. 276–279). EDAA. http://hdl.handle.net/20.500.12708/54574
  • Efficient Radiation-Hardening of a Muller C-Element / Veeravalli, V. S., & Steininger, A. (2012). Efficient Radiation-Hardening of a Muller C-Element. In 2012 Single Event Effects Symposium. 2012 Single Event Effects Symposium (SEE 2012), San Diego, USA, Non-EU. http://hdl.handle.net/20.500.12708/54573
  • Radiation-Tolerant Combinational Gates - An Implementation Based Comparison / Veeravalli, V. S., & Steininger, A. (2012). Radiation-Tolerant Combinational Gates - An Implementation Based Comparison. In Design and Diagnostics of Electronic Circuits Systems (DDECS), 2012 IEEE 15th International Symposium on (pp. 115–120). http://hdl.handle.net/20.500.12708/54570
  • Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation / Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2012). Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation. In Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12). 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12), Biarritz, FRANCE, EU. http://hdl.handle.net/20.500.12708/54565
  • Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip / Veeravalli, V. S., Steininger, A., Schmid, U., & Polzer, T. (2012). Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. In Proceedings 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD’12) (pp. 8–17). http://hdl.handle.net/20.500.12708/54564
  • Protecting an Asynchronous NoC against Transient Channel Faults / Naqvi, S. R., Veeravalli, V. S., & Steininger, A. (2012). Protecting an Asynchronous NoC against Transient Channel Faults. In Proc. of 15th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/54503

2011

  • Replicated processors on a single die - How independently do they fail? / Steininger, A., & Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E & i, 128(6), 245–250. https://doi.org/10.1007/s00502-011-0005-9
  • Automated test-trace inspection for microcontroller binary code / Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., & Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). http://hdl.handle.net/20.500.12708/54078
    Project: CEVTES (2010–2013)
  • VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation / Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. https://doi.org/10.1155/2011/936712
    Project: DARTS (2005–2010)
  • Hardware support for efficient testing of embedded software / Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., & Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, Non-EU. ASME. http://hdl.handle.net/20.500.12708/54082
    Project: CEVTES (2010–2013)
  • Past Time LTL Runtime Verification for Microcontroller Binary Code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-24431-5_5
    Project: CEVTES (2010–2013)

2010

  • Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). http://hdl.handle.net/20.500.12708/53554
    Project: CEVTES (2010–2013)
  • Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/ahs.2010.5546277
  • Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. https://doi.org/10.1109/dsnw.2010.5542609
  • A deterministic approach for hardware fault injection in asynchronous QDI logic / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. https://doi.org/10.1109/ddecs.2010.5491758
  • Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776

2009

2008

  • Towards a Systematic Test for Embedded Automotive Communication Systems / Armengaud, E., Steininger, A., & Horauer, M. (2008). Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Transactions on Industrial Informatics, 4(3), 146–155. https://doi.org/10.1109/TII.2008.2002704
    Project: STEACS (2003–2008)
  • Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras / Ambrosch, K., Humenberger, M., Kubinger, W., & Steininger, A. (2008). Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. In 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR ’08, Anchorage, Alaska, USA, Non-EU. https://doi.org/10.1109/cvprw.2008.4563146
  • Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems / Forster, W., Kutschera, C., Steininger, A., & Göschka, K. M. (2008). Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems. In Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008) (pp. 1–8). IEEE Computer Society. http://hdl.handle.net/20.500.12708/52268
  • Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks / Milbredt, P., Steininger, A., & Horauer, M. (2008). Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. In 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008). IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong, Non-EU. https://doi.org/10.1109/delta.2008.74
  • Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems / Armengaud, E., Függer, M., & Steininger, A. (2008). Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems. In 2008 IEEE International Workshop on Factory Communication Systems. WFCS, Torino, Italy, EU. https://doi.org/10.1109/wfcs.2008.4638707
    Project: EXTRACT (2005–2008)
  • An investigation of the clique problem in FlexRay / Milbredt, P., Horauer, M., & Steininger, A. (2008). An investigation of the clique problem in FlexRay. In 2008 International Symposium on Industrial Embedded Systems. SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France, EU. https://doi.org/10.1109/sies.2008.4577700
  • Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements / Grahsl, J., Handl, T., & Steininger, A. (2008). Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements. In 20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen (pp. 165–169). http://hdl.handle.net/20.500.12708/52459
    Project: DARTS (2005–2010)
  • Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip / Fuchs, G., Függer, M., Schmid, U., & Steininger, A. (2008). Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien, EU. IEEE. https://doi.org/10.1109/dsd.2008.65
    Project: DARTS (2005–2010)

2007

  • FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung / Schmid, U., Steininger, A., & Sust, M. (2007). FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung. Elektrotechnik und Informationstechnik : e & i, 124(1–2), 3–8. https://doi.org/10.1007/s00502-006-0409-0
  • Hardware Implementation of an SAD based stereo vision algorithm / Ambrosch, K., Humenberger, M., Kubinger, W., & Steininger, A. (2007). Hardware Implementation of an SAD based stereo vision algorithm. In Proceedings of Third IEEE Workshop on Embedded Computer Vision. Third IEEE Workshop on Embedded Computer Vision, Minneapolis, Non-EU. http://hdl.handle.net/20.500.12708/52065
  • Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits / Schmid, U., Steininger, A., & Veith, H. (2007). Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits. In Fachtagung Zuverlässigkeit und Entwurf (pp. 173–174). VDE Verlag. http://hdl.handle.net/20.500.12708/51805
  • Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems / Horauer, M., Armengaud, E., & Steininger, A. (2007). Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems. In ASME 2007 International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering. International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering (ASME), Las Vegas, Non-EU. http://hdl.handle.net/20.500.12708/52064
    Project: STEACS (2003–2008)
  • A Fail-Silent Reconfigurable Superscalar Processor / Kottke, T., & Steininger, A. (2007). A Fail-Silent Reconfigurable Superscalar Processor. In 13th Pacific Rim International Symposium on Dependable Computing (PRDC’07), Melbourne (pp. 232–239). http://hdl.handle.net/20.500.12708/52063
  • The Effect of Quartz Drift on Convergence-Average based Clock Synchronization / Armengaud, E., Steininger, A., & Hanzlik, A. (2007). The Effect of Quartz Drift on Convergence-Average based Clock Synchronization. In Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation (pp. 1123–1130). http://hdl.handle.net/20.500.12708/52061
    Project: EXTRACT (2005–2008)
  • Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit / Handl, T., Steininger, A., & Kempf, G. (2007). Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit. In Proceedings IDT’07 - The Second International Design and Test Workshop (pp. 115–119). http://hdl.handle.net/20.500.12708/52055
    Project: DARTS (2005–2010)
  • SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis / Grahsl, J., Handl, T., Steininger, A., & Kempf, G. (2007). SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis. In Austrochip - Workshop on Microelectronics (pp. 91–98). http://hdl.handle.net/20.500.12708/52053
    Project: DARTS (2005–2010)
  • Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme / Kottke, T., & Steininger, A. (2007). Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen, EU. http://hdl.handle.net/20.500.12708/51797
  • An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip / Handl, T., Steininger, A., & Kempf, G. (2007). An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 66–70). http://hdl.handle.net/20.500.12708/51796
    Project: DARTS (2005–2010)

2006

  • Automatic Parameter Identification in FlexRay Based Automotive Communication Networks / Armengaud, E., Steininger, A., & Horauer, M. (2006). Automatic Parameter Identification in FlexRay Based Automotive Communication Networks. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 897–904). IEEE. https://doi.org/10.1109/ETFA.2006.355404
    Projects: EXTRACT (2005–2008) / STEACS (2003–2008)
  • Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz / Steininger, A., & Kottke, T. (2006). Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 36–40). http://hdl.handle.net/20.500.12708/51501
  • The DARTS project / Steininger, A. (2006). The DARTS project. ESA Workshop, Aarhus, Denmark, EU. http://hdl.handle.net/20.500.12708/84591
  • The ECS group's hardware related research activities / Steininger, A. (2006). The ECS group’s hardware related research activities. Firma Freescale, München, EU. http://hdl.handle.net/20.500.12708/84590
  • Recovery Mechanisms for Dual Core Architectures / El Salloum, C., Steininger, A., & Tummeltshammer, P. (2006). Recovery Mechanisms for Dual Core Architectures. In 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings (pp. 380–388). http://hdl.handle.net/20.500.12708/51601
  • Implementation of an FPGA-Based Hardware Fault Injector / Handl, T., & Steininger, A. (2006). Implementation of an FPGA-Based Hardware Fault Injector. In Junior Scientist Conference 2006 (pp. 23–24). http://hdl.handle.net/20.500.12708/51572
  • Time-Multiplexed Multiple Constant Multiplication / Tummeltshammer, P., & Steininger, A. (2006). Time-Multiplexed Multiple Constant Multiplication. In Junior Scientist Conference 2006 (pp. 77–78). http://hdl.handle.net/20.500.12708/51570
  • A Practical Comparison of Logic Design Styles / Delvai, M., & Steininger, A. (2006). A Practical Comparison of Logic Design Styles. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3 (pp. 61–66). http://hdl.handle.net/20.500.12708/51530
  • Asynchronous Logic Design - from Concepts to Implementation / Delvai, M., & Steininger, A. (2006). Asynchronous Logic Design - from Concepts to Implementation. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1 (pp. 81–86). http://hdl.handle.net/20.500.12708/51528
  • Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods / Delvai, M., & Steininger, A. (2006). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods. In 9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools (pp. 131–136). http://hdl.handle.net/20.500.12708/51526
  • Pushing the Limits of Remote Online Diagnosis in FlexRay Networks / Armengaud, E., & Steininger, A. (2006). Pushing the Limits of Remote Online Diagnosis in FlexRay Networks. In 6th IEEE International Workshop on Factory Communication Systems. IEEE International Workshop on Factory Communication Systems, Porto, Portugal, Austria. http://hdl.handle.net/20.500.12708/51517
    Project: EXTRACT (2005–2008)
  • A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks / Armengaud, E., & Steininger, A. (2006). A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks. In Junior Scientist Conference 2006. Junior Scientist Conference, Wien, Austria. http://hdl.handle.net/20.500.12708/51516
    Project: EXTRACT (2005–2008)
  • VLSI Implementation of a Fault-Tolerant Distributed Clock Generation / Ferringer, M., Fuchs, G., Steininger, A., & Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). http://hdl.handle.net/20.500.12708/51509
    Project: DARTS (2005–2010)
  • Fault-Tolerant Algorithms on SoCs - A case study / Steininger, A., Függer, M., Schmid, U., & Fuchs, G. (2006). Fault-Tolerant Algorithms on SoCs - A case study. In Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 190–191). http://hdl.handle.net/20.500.12708/51508
    Project: DARTS (2005–2010)
  • Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes / Fuchs, G., Grahsl, J., Schmid, U., Steininger, A., & Kempf, G. (2006). Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes. In Austrochip Mikroelektroniktagung (pp. 149–156). http://hdl.handle.net/20.500.12708/51506
    Project: DARTS (2005–2010)
  • An Efficient Test for a Transition Signalling based Up-/Down-Counter / Függer, M., Handl, T., Steininger, A., Widder, J., & Tögel, C. (2006). An Efficient Test for a Transition Signalling based Up-/Down-Counter. In Austrochip Mikroelektroniktagung (pp. 55–62). http://hdl.handle.net/20.500.12708/51505
    Project: DARTS (2005–2010)
  • Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs / Steininger, A., Handl, T., Fuchs, G., & Zangerl, F. (2006). Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs. In East-West Design & Test International Workshop (pp. 59–64). http://hdl.handle.net/20.500.12708/51504
    Project: DARTS (2005–2010)
  • Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme / Fuchs, G., Függer, M., Steininger, A., & Zangerl, F. (2006). Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme. In WDES 2006 3rd Workshop on Dependable Embedded Systems (pp. 22–27). http://hdl.handle.net/20.500.12708/51503
    Project: DARTS (2005–2010)
  • A Reconfigurable Generic Dual-Core Architecture / Kottke, T., & Steininger, A. (2006). A Reconfigurable Generic Dual-Core Architecture. In Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 45–54). http://hdl.handle.net/20.500.12708/51502
  • Teaching Hardware Software Codesign to Software Engineers / Delvai, M., & Steininger, A. (2006). Teaching Hardware Software Codesign to Software Engineers. In International Workshop on Reconfigurable Computing Education. 1st International Workshop on Reconfigurable Computing Education, Karlsruhe, EU. http://hdl.handle.net/20.500.12708/51473

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  • Generic microprocessor-controlled test unit / Hofer, M. (2010). Generic microprocessor-controlled test unit [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159779

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